(a) Field of the Invention
The present invention relates to a PLL (phase locked loop) synthesizer and, more particularly, to a PLL synthesizer which is capable of selecting one of a plurality of locking times in a cellular phone.
(b) Description of the Related Art
PLL circuits are widely used in the fields of, for example, television receivers, satellite communications, and radio communications. The PLL circuit generates a frequency signal in synchrony with a reference signal having a reference frequency, the frequency signal having a frequency of a specified ratio with respect to the reference frequency. For example, in a cellular phone system operating with a time division multiple access (TDMA) scheme, the PLL circuit is used as a PLL synthesizer which generates the frequency of a transmission channel.
FIG. 6 shows a conventional PLL synthesizer, which includes a PLL integrated circuit (PLL-IC) 20, a first loop filter (LPF) 40, a second loop filter (LPF) 45, and a voltage controlled oscillator (VCO) 50. The PLL-IC 20 includes therein a phase comparator 24, a register 23, a divider 22, a prescaler 21, and a charge pump (CP) 25.
An output of the VCO 50 is delivered to outside the PLL synthesizer as well as the prescaler 21 to form a feedback loop. The prescaler 21 has a function of roughly dividing the input frequency with a high speed to assist the dividing operation by the divider 22. The divided-frequency signal 104 output from the divider 22 and the reference frequency signal (Ref_F) 100 are fed to the phase comparator 24. The phase comparator 24 compares phases of both the input signals against each other to deliver a phase comparison result signal which depends on which phase leads or lags with respect to the other. The charge pump 25 receives an output signal from the phase comparator 24 to deliver an output voltage signal to the VCO 50 through the LPF 40 and the loop filter 45. The output frequency of the VCO 50 is controlled by the output voltage signal of the charge pump 25. Upon coincidence of the phase of the divided-frequency signal 104 with the phase of the reference frequency signal 100, the PLL synthesizer is locked, i.e., the oscillation frequency of the PLL synthesizer is fixed at a desired frequency.
The loop filter 45 is provided in order to control the locking time of the PLL synthesizer, i.e., the time interval between the time instant at which the change of the oscillation frequency of the PLL synthesizer is started and the time instant at which the PLL synthesizer is locked to stabilize the oscillation frequency. The time constant of the loop filter 45 is set to conform with the locking time needed in the PLL synthesizer. For example, if the frequency should be switched at a higher speed, then the time constant is set at a lower value, and if the frequency need not be switched at a high speed, then the time constant is set at a larger value to obtain a longer locking time.
For reducing the locking time, the time constant of the loop filter should be reduced. However, a smaller time constant increases the bandwidth of the loop filter and degrades the carrier-to-noise (C/N) ratio of the signal passing therethrough, degrading the characteristics of the radio system having the PLL synthesizer.
If the PLL synthesizer has a configuration such that the output frequency thereof is changed stepwise, the time constant of the loop filter 45 should be set at a value corresponding to the minimum locking time necessary in the changeover for a specified output frequency. However, setting of the locking time at the value corresponding to the minimum locking time means that the minimum locking time is used in the changeover of all the other output frequencies wherein such a minimum locking time is not necessary. This means the PLL synthesizer is used in the state of degraded C/N ratio in all the other output frequencies due to achieving the shorter locking time thus selected. In short, a smaller locking time and better radio characteristics are tradeoffs in the conventional PLL synthesizer.
In view of the above, it is an object of the present invention to provide a PLL synthesize capable of achieving a required locking time and an excellent C/N ration in the output frequency thereof.
It is another object of the present invention to provide a cellular phone having a plurality of slots in a single frame and achieving an optimum locking time in the switching between the plurality of frequencies used in respective slots in the single frame.
The present invention provides a phase locked loop (PLL) synthesizer including: a phase comparator for comparing a phase of a first frequency signal having a first frequency against a phase of a reference frequency signal; a voltage controlled oscillator (VCO) having an input node receiving a frequency control voltage controlled based on a result of the comparison by the phase comparator, and an output node outputting a second frequency signal having a second frequency controlled based on the frequency control voltage; a frequency divider for receiving the second frequency signal to divide the second frequency and to output the first frequency signal; and a loop filter connected at the input node of the VCO for passing the frequency control signal to the VCO, the loop filter having three or more time constants for a filter function and a selector for selecting one of the time constants.
The present invention also provides cellular phone including the PLL synthesizer as defined in claim 1, wherein the cellular phone has three or more slots in a single frame.
In accordance with the PLL synthesizer of the present invention and the PLL synthesizer in the cellular phone of the present invention, an optimum time constant can be obtained in the PLL synthesizer for achieving an optimum locking time and excellent characteristics of the cellular phone having the PLL synthesizer.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.